KO
TIPS,
TRICKS
TRAPS
S-24C SERIES EEPROMs
&
Seiko Instruments Inc.
Contents
1. Tip: Add a pull-up resistor to the input terminals ............... 1
2. Tip: First match the phase to reset the EEPROM.............. 1
Tip: How to reset the EEPROM ......................................... 2
3. Tip: Acknowledge check.................................................... 3
4. Tip: Applying the supply voltage........................................ 3
4-1. To secure correct operation of power-on clear circuit .. 3
5. Trap: Problems in the power-on clear circuit ..................... 5
6. Trap: Wait for the initialization sequence to complete....... 5
7. Trap: Delay the SDA line to avoid errors due to noise....... 6
8. Trap: Severe environments ............................................... 7
1
TIPS, TRICKS, & TRAPS WHEN USING THE S-24C SERIES
EEPROMs
This application note describes tips, tricks, and traps to help the
design engineer prevent errors and get maximum performance when
using Seiko Instruments S-24C series EEPROMs.
All EEPROMs (from any manufacturer) may experience a
"
write
"
error
due to:
operation in a low voltage region during power-on / power-off;
noise signals causing an error in acknowledging an instruction.
These errors frequently occur when the operating voltage drops below
the microcomputer
'
s minimum operating voltage. Based on the
manufacturer
'
s circuit design, certain steps can be taken by the
designer to prevent these errors.
1. Tip: Add a pull-up resistor to the input terminals.
Add a 1K to 5K ohm pull-up resistor to the:
SCL input terminal, and the
SDA I/O terminal
in order to enable the functions of the I
2
CBUS protocol. This is
necessary to prevent errors caused by an undefined output (high
impedance applied to the input terminal). This can occur when the
MCU is reset at a low voltage.
Normal communication cannot be provided without a pull-up resistor.
2. Tip: First match the phase to reset the EEPROM.
The S-24C series does not have a reset terminal. If there is a power
interruption, and the MCU resets, the phase (clock timing) of the
EEPROM must first be matched to the phase of the MCU. After the
phase is matched, reset the EEPROM using start and stop
instructions.
2
Tip: How to reset the EEPROM
If the EEPROM is reading data "0", or outputting an acknowledge
signal, then it is outputting "0" to the SDA line, and the microprocessor
must not send instructions to the SDA line. In this case, first terminate
the acknowledge outputting operation or the read operation. Then
enter a start condition freshly, Refer to Figure 1.
Send SCL for nine dummy clocks:
The microcomputer maintains the SDA line at a
"
high
"
level;
The EEPROM aborts the acknowledge data output;
During this time, input a
"
start
"
condition.
Now the EEPROM is reset (after the
"
start
"
condition).
Next, input a
"
stop
"
condition, and the EEPROM will restore normal
operation.
SCL
SDA
Dummy clock
1
2
8
9
Start condition
Stop condition
FIG. 1 Resetting the EEPROM
Be sure to input a start condition after the nine dummy clocks. A write
operation may be executed upon receipt of a stop condition, if no start
condition has been applied to the SCL clock line.
To achieve perfect reset operation, use the above
"
dummy clock reset
method
"
after the supply voltage has been applied according to Tip 4
below.
3
3. Tip: Acknowledge check.
I
2
CBUS protocol has an "acknowledge check" handshake to avoid
communication errors. To prevent communication errors, be sure to
execute the "acknowledge check" in the microcomputer.
4. Tip: Applying the supply voltage
Seiko Instruments EEPROMs have a built-in
"
power-on clear
"
circuit.
The power-on clear circuit is one that initializes the IC when the supply
voltage is raised, for purposes of avoiding false operations. Follow the
procedure below to apply the supply voltage in a safe manner.
4-1. To secure correct operation of power-on clear circuit
Starting at a maximum of 0.2V as shown in Figure 2, increase the
supply voltage to your operating value within the time frame t
rise
. Note
that the value of t
rise
will change depending on your operating voltage
(Figure 3).
For example:
If your EEPROM supply voltage = 5.0V,
t
rise
= 200 msec (from Figure 3),
increase the V
cc
to 5.0V within 200 msec (Figure 2).
4
0.2v
0v (Note1)
trise (max)
Power voltage VCC
Vinit (max)
tinit(max) (Note2)
Note 1:
"
0V
"
means there is no difference in potential between the
V
cc
terminal and the GND terminal of the EEPROM.
Note 2: t
init
is the time required to initialize the EEPROM. No
instructions are accepted during this time.
Figure 2. Increase of the Supply Voltage
VCC (v)
5.0
(msec)
t
rise
(max)
200
50
150
100
4.0
3.0
2.0
Figure 3. VCC vs t
rise
(max)
5
5. Trap. Problems in the power-on clear circuit.
Once the power-on clear circuit has been used to complete
initialization, the EEPROM is set to a standby condition. If the power-
on clear circuit does not operate properly, here is a potential problem:
The EEPROM has not been initialized properly. In this case, a
previous input instruction may still be valid, or an instruction may be
improperly acknowledged. A write error may occur. (Refer to Section
2.)
6. Trap: Wait for the initialization sequence to complete.
The EEPROM executes initialization during the time that the supply
voltage is increasing to its normal value. All instructions must wait
until after initialization. The relation between initialization time (t
init
)
and rise time (t
rise
) is shown in Figure 4.
t
rise
(seconds)
t
init
(seconds)
1m
1
100
10
10m 100m
1
10
100
1m
10m
100m
FIG. 4 t
init
vs. t
rise
For example, it will take some 20
sec of t
init
when the supply voltage
is raised in 10
sec.
6
7. Trap: Delay the SDA line to avoid errors due to noise.
For the S-24C series, delay the SDA line by at least 300 nanoseconds
from the falling edge of the SCL line. Here
'
s why:
This is intended to prevent the STOP (or START) condition from
taking place because of slippage in the timing (due to the parasitic
capacitance of the bus line, etc.)
Consider the case when the SDA & SDL lines are changing at the
same time. In this case, noise can activate the start/stop sequence.
The EEPROM will switch to standby, and communication will be lost.
See Figure 5.
SCL
SDA
tHD.DAT = 300ns max
FIG. 5 EEPROM Data Input Hold Time
min.
7
8. Trap: Severe environments.
Absolute maximum ratings: Do not operate these ICs in excess of the
absolute max ratings, as listed on the data sheet. Exceeding the
supply voltage rating can cause latch-up.
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